{"license":"Free for any use with attribution link to rfid-datasheet.com","citation":"RFID-Datasheet.com Chip Database — Roxtron","source":"https://rfid-datasheet.com/chip/smartmx2-p60","methodology":"https://rfid-datasheet.com/methodology","data_notes":"Includes automated enrichment. Null means unknown; last_checked is link availability, not technical review. Manufacturer documents govern specifications.","generated_at":"2026-11-01T19:50:18.976Z","chip":{"id":"d5e66818-576c-4351-9359-592f2ee1cd03","slug":"smartmx2-p60","name":"SmartMX2 P60","manufacturer":"NXP","frequency_category":"HF 13.56 MHz","short_description":"Dual-interface secure smart card controller, CC EAL6+","manufacturer_url":"https://www.nxp.com/docs/en/data-sheet/SMX2_FAM_P60D080_D144_SDS.pdf","frequency":"13.56 MHz","protocol":"ISO/IEC 14443 Type A, ISO/IEC 7816 (T=0, T=1)","memory":"P60D080: 80 KB EEPROM, 384 KB ROM, 8.125 KB RAM / P60D144: 144 KB EEPROM, 384 KB ROM, 8.125 KB RAM","interface":"Dual interface: ISO/IEC 7816 contact + ISO/IEC 14443A contactless (RF), supports data rates 106/212/424/848 kbit/s","temp_range":"-25°C to +85°C","form_factor":"Wafer (150 μm / 75 μm), MOB4/MOB6 contactless modules, PDM1.1 dual interface modules (8-contact)","security":"Common Criteria EAL6+ certified, AES, Triple-DES, RSA/ECC (Fame2 coprocessor), True RNG (AIS-31), active shielding, glue logic layout, sensors (voltage/temperature/light/frequency/SFI), MMU with System/User modes, encrypted memory, unique ID optional, 3DES, secure code execution integrity","use_cases":["payments-transit","access-control"],"engineering_brief":"The NXP SmartMX2 P60D080/P60D144 are dual-interface secure smart card controllers fabricated in 90 nm CMOS, offering contact (ISO/IEC 7816) and contactless (ISO/IEC 14443A) operation with full concurrent interface support. The chips feature 80 KB or 144 KB EEPROM, 384 KB ROM, enhanced SmartMX2 CPU, and dedicated crypto coprocessors: Fame2 for RSA/ECC public key operations and SBC for AES/Triple-DES symmetric encryption. Common Criteria certified with extensive physical and logical countermeasures including active shielding, glue logic layout, multi-level sensors, MMU-based memory protection, and secure code execution, these controllers are designed for high-security government ID, banking, and multi-application smart card deployments requiring state-of-the-art protection and performance.","enriched":true,"url_status":"ok","link_status":"valid","last_checked":"2026-11-01T03:31:28.371+00:00","last_status_code":200,"last_content_type":"application/pdf","created_at":"2026-06-14T16:30:56.111445+00:00","manufacturer_id":"6daaf1cc-d0e6-40c7-aba0-a08b4c3493fe","chip_type":"secure_element","dual_interface":false,"is_family_hub":false,"meta_description":"NXP SmartMX2 P60 dual-interface secure element with 80/144 KB EEPROM, EAL6+ certification, AES/RSA/ECC crypto, and ISO 14443A + ISO 7816 support for government ID and banking.","faq":[{"a":"The SmartMX2 P60 is certified to Common Criteria EAL6+, one of the highest security assurance levels available for smart card controllers. This certification validates the chip's resistance to sophisticated physical and logical attacks.","q":"What is the Common Criteria certification level of the NXP SmartMX2 P60?"},{"a":"Yes, the P60 is a dual-interface controller supporting both ISO/IEC 7816 contact and ISO/IEC 14443 Type A contactless (13.56 MHz) interfaces with full concurrent operation. Contactless data rates of 106, 212, 424, and 848 kbit/s are supported.","q":"Does the SmartMX2 P60 support both contact and contactless interfaces?"},{"a":"The P60D144 variant includes 144 KB of EEPROM for user data and applets, 384 KB ROM for operating system and libraries, and 8.125 KB RAM. The P60D080 variant offers 80 KB EEPROM with the same ROM and RAM.","q":"How much memory does the SmartMX2 P60D144 have?"},{"a":"The P60 features dedicated crypto coprocessors for AES, Triple-DES (3DES), RSA, and ECC. The Fame2 coprocessor handles public key operations while the SBC handles symmetric encryption, and a True RNG compliant with AIS-31 provides secure random number generation.","q":"What cryptographic algorithms does the SmartMX2 P60 support?"},{"a":"The P60 incorporates active shielding, glue logic layout, voltage/temperature/light/frequency sensors, and secure flash interface monitoring. These countermeasures protect against side-channel analysis, fault injection, and invasive physical attacks.","q":"What physical security features does the SmartMX2 P60 include?"},{"a":"The P60 is designed for high-security applications including government-issued electronic ID documents (ePassports, national ID cards), EMV payment cards, banking smart cards, and multi-application platforms requiring EAL6+ certified protection and dual-interface capability.","q":"What applications is the NXP SmartMX2 P60 designed for?"}],"standards":["iso-14443a","iso-7816","nfc-forum-type-4"],"alternatives":null,"no_direct_competitor":false,"long_form_html":null,"og_image_url":null,"canonical_url":"https://rfid-datasheet.com/chip/smartmx2-p60"}}